Abstract or Demonstration Description: To support future performance increases and to boost yield of large and complex digital devices, there is a growing trend to assemble them from several chiplets in one package instead of using just one large monolithic die. This enables devices with an overall size much bigger than the maximum reticle size and allows to combine chiplets originally manufactured in different process nodes. Interconnection between the chiplets is typically made with wide, short-reach interfaces like HBM for memory and UCIe for a compute die. These die-to-die interfaces are optimized to deliver a high bandwidth over a short (few mm) connection at minimal power consumption. For various reasons (number of signals, probe pitch, drive strength etc.) they are not suitable to connect to an ATE channel. Instead, they rely on sophisticated BIST and loopback schemes for testability in production. In the future, we will see chiplets where most or all external access ports are not suitable for connecting to an ATE. But they will still require high-bandwidth test access especially in wafer sort to support known good die (KGD) approaches: Scan test is the primary coverage guarantee for digital logic and needs data volumes which by far exceed the capabilities of a remaining narrow and slow iJTAG port. Already today, some manufacturers rely on sacrificial pads for test access in wafer sort to overcome this problem: A number of pads with a probe-friendly pitch and strong I/O cells are exclusively used for test access in sort and not connected in package. This guarantees the required test access and does not impact the die-to-die interfaces. This paper will give a brief overview of the new UCIe standard for chiplets and related DfT and BIST features. It will also elaborate on a proposal for a dedicated test port for ATE connection to chiplets. References to recently developed scan bus architectures will be made as well as a connection to the IEEE 1838 standard for 3D IC test which proposes a flexible parallel port (FPP) as path for high-bandwidth test access in volume production.