Vice President of Engineering Elevate Semi San Diego, California, United States
Abstract or Demonstration Description: The primary concern for customers of ATE companies is the cost of test. Tester manufacturers have been able to reduce costs in the past by integrating discrete devices and increasing functionality and channel count through ATE specific IC's. Subsequently, ATE IC's have focused on power and area to increase tester channel density, leading to the next generation of cost reductions through parallelization.
However, as technical innovation continues to grow in multiple dimensions, such as increasingly complex protocols and standards, increasingly higher and lower extremes in voltages and currents, combined with ever increasing speeds, the low-hanging fruits have disappeared, leading to increasingly complex and competing demands. While some solutions may offer performance at any cost, this approach is only a temporary fix that is not scalable.
To address these challenges, it is essential to collaborate, innovate, and capitalize on the extremely complex and fast-moving future that our customers desire. We must find ways to provide reduced costs that will foster innovation and allow Moore's law to continue to advance.