Abstract or Demonstration Description: Latch-up testing of integrated circuits is usually run on dedicated latch-up systems. The present generation of high power devices are rapid outstripping the capacities of these dedicated testers. This presents an opportunity to run these devices on the more flexible ATE platforms.
The latch-up test begins by starting the device in a stable and reproducible “low” power state. This low power state can require dozens of amperes. It is also one of the areas the traditional latch-up testers are being rapidly outstripped; They can deliver a maximum current of 18 Amps with their internal supplies. Yet, our laboratories are beginning to see analysis requests for devices requiring hundreds of Amps on a single channel.
Even when the power required is within the tester’s design range, it still needs to be properly distributed among the power rails. Many of the devices we are seeing have a few dozen power domains. For proper granularity of testing, they all should be kept independent from one another. This is far beyond the capabilities of dedicated latch-up testers, which can only bias seven independent power domains.
Beyond these power issues, larger devices simply have far more pins than the current generation of latch-up testers possess. These testers are designed for devices up to 2304 independent pins, while we are now seeing requests for devices in the 10,000 pin range.
This paper will discuss the above issues, DUT board design considerations for the ATE and present real world data from parts in the 50-200 watt range. This data is from successful JEDEC 78, Rev E latch-up testing on high power, large pin count devices, on an ATE tester. The paper will conclude with a brief discussion of the upcoming latch-up challenges that can be addressed with in-house, ATE hardware.