The semiconductor industry’s move toward advanced packaging technologies has been fueled by the plateau of Moore’s Law. As the need for transistor density goes up, so does the need for advanced packaging technologies such as 2.5D, 3D-IC, and fan-out wafer-level. One major factor to consider with advanced packaging is the integrity of the chips themselves. One “bad” die could result in the malfunctioning of an entire system making it crucial that only known good die (KGD) are used in advanced packages. Therefore, a process and shipping carrier that can secure known good bare die is needed. Pocketed trays are commonly used as carriers; however, they have recognized risk of die damage and loss due to rattling and out of pocket events. This thereby leads to costly rework. Tacky carriers can secure devices but die removal from a tacky surface requires optimized process parameters in order pick die quickly without damage. Using a Royce Instruments AP+ we were able to easily determine the pick parameters necessary for successful picking of small 250 um wide die up to 2-inch-wide die from Gel-Paks. In addition, picking parameters for 50um thick silicon dies was determined. In all cases, vacuum pressure on the tray was not needed. The ideal pickup force and pick speed windows were determined. Key considerations on tool leveling and pick up tool design facilitated successful picking. In addition, optimization of die blow-off allowed for easy and precise die orientation when placing onto a Gel-Pak vs die out of pocket with Waffle pack trays.
