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The buildup of wafer fabs to support a $1TB semiconductor industry by 2030 is on everyone's mind. Testing innovation and factory test cell integration is the path to 1TB. The frontend wafer fabrication process is only "halfway there" toward a fully functional device that meets performance, quality, and cost requirements. The chips must still be tested, packaged, and tested again throughout the backend integration processes.
Session Moderator: Jeorge S. Hurtarte, PhD, MBA – Teradyne
Session Moderator: Alan Liao – FormFactor
Session Moderator: Paul Berndt, MSEE, CID+ – Microsoft Corporation
Keynote Speaker: Regan Mills, MS – Teradyne, Inc.
Session Moderator: Rich L. Dumene – Reneasas
Speaker: Bob Bartlett – Advantest Corporation
Speaker: Alan Hart – Advantest America
Co-Presenter: Greg Prewitt – PDF Solutions
Speaker: Ken Butler, PhD – Advantest
Speaker: Martin Stadler – Teradyne
Co-Presenter: Dan Thornton – Teradyne
Session Moderator: Ken Lanier, BSEE – Teradyne
Speaker: Keith Schaub, MSEE – Advantest
Speaker: Jack DeGrave, PhD – FormFactor
Co-Presenter: Brandon W. Boiko, MS – FormFactor
Co-Presenter: Phoenix Dai – FormFactor
Speaker: Higor Rodrigues Batagin – SPEA S.p.A.
Speaker: Richard W. Fanning – Teradyne