Consultant
Kearney
Trophy Club, TX, United States
Previously Director of Lithography at Intel.
*Co-Inventor of novel VWF circuits for power management in High-efficiency, low leakage transistors for Big data (Servers) and AI interfaces.
*Co-Inventor of Gate-fill 3D doping process for Servers/Big data processor design.
*Inventor of BA/SA-120 TRIP-induced strength modelled alloys using the revolutionary Computational Modelling and Dynamics approach to Materials Design and Manufacturing
Expert in advanced Semiconductor Product design and manufacturing, including 7nm Metal Gate process. Managed cross-site multi-disciplinary teams for New Product Introduction and delivered flawless manufacturing and product launch for Intel server products.
Disclosure information not submitted.
Supply Chain Management for the Semiconductor Fab of the Future
Thursday, July 13, 2023
3:15 PM – 3:35 PM PDT