Test Vision: Test Innovation Enables the Path Forward ( Day 2 of 2)

The buildup of wafer fabs to support a $1TB semiconductor industry by 2030 is on everyone's mind. Testing innovation and factory test cell integration is the path to 1TB. The frontend wafer fabrication process is only "halfway there" toward a fully functional device that meets performance, quality, and cost requirements. The chips must still be tested, packaged, and tested again throughout the backend integration processes.

Presentations:

• 9:00 AM – 9:05 AM PDT

  Opening Remarks
  

  Session Moderator: Jeorge S. Hurtarte, PhD, MBA – Teradyne
• 9:10 AM – 9:55 AM PDT

  Heterogeneous Integration Paving the way for Microelectronics Resurgence
  

  Keynote Speaker: William Chen, PhD – Heterogeneous Integration Roadmap, IEEE EPS
• 9:55 AM – 10:00 AM PDT

  Session III: Introduction
  

  Session Moderator: Adrian Kwan, In the Semiconductor Test industry for over 20 years, Adrian Kwan, Senior Business Development Manager drives the company Global RF/Wireless Market Segment, based in Advantest American Inc, San Jose. He works with the sales team to drive business strategies and solutions to customers globally. With deep knowledge in the RF and Microwave technologies, he also works closely with Product Marketing and R&D to define RF/mmWave ATE solutions to address current and future technology in this market space. For leisure, I enjoyed hiking, swimming, scuba diving, and being outdoors. – Advantest America Inc.
• 10:00 AM – 10:25 AM PDT

  Production Test RF Calibration Methods for Probe Cards
  

  Speaker: Pratik Ghate – FormFactor
• 10:25 AM – 10:50 AM PDT

  ATE Latch-up Testing of Real World, High Power Devices
  

  Speaker: charles watson, PhD – ISE Labs, Inc.
• 10:50 AM – 11:15 AM PDT

  Getting the Straight Story: Approaches to Linearity Measurements for ADCs
  

  Speaker: Jack Arnold – National Instruments
• 11:40 AM – 12:05 PM PDT

  Emerging PMIC Trends Demand Test Innovations
  

  Speaker: Lauren Getz – Teradyne
• 12:05 PM – 12:30 PM PDT

  Test Vision - Program Chair Remarks
  

  Session Moderator: Robert Schneider – Advantest
• 1:00 PM – 1:55 PM PDT

  CHIPS Act Implementation: Past, Present, and Future - mySilicon Compass
  

  Keynote Speaker: Travis Mosier, MA – mySilicon Compass
• 1:55 PM – 2:00 PM PDT

  Session IV: Introduction
  

  Session Moderator: Stuart Pearce – AEM
• 2:00 PM – 2:25 PM PDT

  HVM test of UCIe-enabled chiplets for 2.5D and 3D devices: The case for a dedicated test port
  

  Speaker: Michael Braun – Advantest Europe GmbH
• 2:25 PM – 2:50 PM PDT

  Advancing Probe Card Parallelism for SOC Devices
  

  Speaker: Cameron Harker – FormFactor
• 2:50 PM – 3:15 PM PDT

  Mixed-Signal Test Workforce Development - An analysis of the Test Program at Texas A&M University
  

  Speaker: Rainer Fink, PhD – Texas A&M University

  Speaker: Thomas Munns – Texas A & M
• 3:15 PM – 3:40 PM PDT

  Enabling Comprehensive, ATE Class, High-performance Protocol Validation on the Bench
  

  Speaker: Saravana Kumar Muthusamy – Soliton Technologies Private Limited

  Speaker: Santhosh Ramaraj – Soliton Technologies
• 3:40 PM – 4:50 PM PDT

  Panel Discussion: From Assembly Line to Field: The Future Semiconductor Testing
  

  Panel Session Moderator: Anne Meixner, PhD – semiengineering.com

  Panelist: Tom Katsioulas – Archon Design Solutions, Inc.

  Panelist: Marisa Russell, BS Chem E – Intel

  Panelist: Ming Zhang, PhD – PDF Solutions

  Panelist: Uzi Baruch – proteanTecs
• 4:50 PM – 4:55 PM PDT

  Symposium Raffle and Winner Announcement
  

  Session Moderator: Junko Nakaya – Advantest America
• 4:55 PM – 5:00 PM PDT

  Closing Remarks
  

  Session Moderator: Jeorge S. Hurtarte, PhD, MBA – Teradyne