Director in Wafer Level Assembly and Package Technology Development
Intel
Chandler, AZ, United States
Morgan Tribolet is a Director in Wafer Level Assembly and Package Technology Development at Intel. She has worked in Assembly/Packaging for more than 18 years. She started her career in 2005 after graduating from the University of Arizona with a Materials Science Engineering degree. She holds patents in Thru Glass Via (TGV) architectures and package warpage control. She has developed and certified many industry leading technologies for Intel including halogen free packaging, Polymer Thermal Interface Material (PTIM), singulated die sort and multi-chip Foveros. Most recently she led the certification of Intel’s most complex packaging technology, Ponte Vecchio, which integrates Intel EMIB technology with Foveros. Morgan was a pioneer in the development of Intel’s wafer stacking technology, ramping their chip to wafer capability to full reticle, active base and 36um pitch. She was an integral member of the design team and her early insights led to key design rules which provide solutions for yield, quality and reliability.
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Heterogeneous Integration Process Development and its Challenges
Wednesday, July 12, 2023
2:40 PM – 3:10 PM PDT