Abstract or Demonstration Description: There are many HPC/AI devices in production today and some of these high gate count, high power devices in single site are testing in HVM on ATE power supplies at over 1,000A. What’s next in the progression; in the range of 2,000A’s for a single Device Under Test (DUT). These requirements present a challenge to everything in the wafer and package device test technology stack up. We will cover all the aspects to consider for ATE testing of HPC devices with main power rails needing up to 2,000A as well as probe protection best known practices, as well as thermal management and PDN discussion. We will discuss device power supply implementation with XPS265 or UHC4T and the potential impact on the performance for each. Key elements will include power feedback loops and sensing, safety monitoring, and profiling. We need to define PDN performance metrics based on device power rail requirements. Additionally, wafer and final test DUT interfaces must be designed with thermal modeling and simulation for reliable operation in HVM and characterization. For the DUT PCB we’ll provide a review of key Power Distribution Network (PDN) and thermal layer design considerations. These include power plane stack-ups, optimized via structure recommendations, design and thermal simulation notes, bulk capacitor selection, and dynamic bulk capacitance control. Will include a look at dynamic response data from 800-1600A for XPS and UHC supplies. As part of the power eco-system, we’ll look at probe and socket thermal performance today and the near future. This will be a how-to guide for deployment of 2,000A ATE power supply solutions for HPC class device testing.
