In addition to improved transistors, interconnects, advanced use of Design technology Co-Optimization and application of advanced packaging and System Technology Co-Optimization, scaling is a key component to the continued improvement of semiconductor product performance. Scaling improves product performance by enabling lower capacitance and lower power systems, by enabling more functionality per logic block by use of additional transistors and by enabling either more cores or memory capacity per chip. Scaling is enabled by innovations in patterning, power delivery and transistor architecture. Stacked transistor architecture is expected to follow gate-all-around architecture for continued improvement in performance and density. Stacked transistor architecture has many processing challenges including high aspect ratio processing capabilities. Stacked transistor architecture will require aggressive metal & Via pitch scaling. Variation control is the key challenge to pitch scaling as the edge placement margin of error is small and the large number of features required for modern circuits implies stochastics sampling in the greater than 7 sigma regime. Solutions are needed to address each component of variation including line roughness and size variation, via size variation, line-end pullback and overlay. Lithography tools, metrology and mask making all critical for tight overlay. High NA EUV essential for efficient & cost-effective scaling moving forward. Multi-pass low-NA EUV approaches can meet pitch targets but add process cost and complexity. Multi-pass patterning approaches result in multiple alignment populations and degraded overlay. High NA has potential to provide 0.6X better resolution and variability vs current EUV tooling but new resist materials, lithography stacks & etches are needed to fully realize this potential. Directed Self-Assembly (DSA) applied with rectification of EUV guide patterns enables fundamental low variability tight pitch lines and when coupled with a multi-mask EUV pitch division process can provide variable design flexibility for metal layer patterning .