(HVM) beginning at the 7nm node logic, and is being qualified at for an increasing proportion of litho steps at 5/3nm Logic and 16/14nm DRAM. A persistent challenge for the EUV scanner is to supply to the photoresist (PR) a high contrast image with enough photons to meet HVM productivity targets with acceptable dimensional and defectivity control. Local stochastic variability in dimension and placement dominates the total dimension control budget, and reducing that variability by increasing the exposure dose comes at the high cost of reducing scanner throughput.
EUV scanner power and reliability have each made significant improvements toward performing at the HVM level over the last 10 years; however photoresists have not kept pace with the increasingly stringent technology requirements. Today spin-on photoresists are unable to meet the resolution, line edge roughness, sensitivity (dubbed the RLS triangle) and defectivity targets for the high volume manufacturing of the most advanced technology nodes. This gap in photoresist readiness has driven customers to make compromises in design and cost and put significant pressure on downstream processes to correct for shortcomings in the lithography pattern, providing a significant opportunity for breakthrough innovation.
We discuss here our revolutionary technique to both apply EUV photoresist and develop latent images in the photoresist using dry technologies instead of the existing wet spin coating and development that have been in use for the last several decades. We will review the key mechanisms and advantages of dry resist processing over wet resist processing, and will report the latest results across a variety of key indices. It will be shown that dry resist technology has demonstrated best-in-class resist performance at leading edge design rules, making possible the hoped-for performance and cost advantages of EUV lithography patterning.
