Heterogenous design and integration has been referred to as the fourth stage of the evolution of Moore’s Law, as it enables simultaneous improvements in power, performance, and area-cost. The expected performance and cost improvements from traditional Moore’s Law scaling have slowed down as we reach the limits of cost-effective monolithic scaling across most computing architectures. As Moore’s law slows down, die size needs to increase to improve performance which is becoming one of the key limiters for yield and is at risk of hitting the reticle limit. Heterogeneous designs enable us to overcome the critical issue of yield and reticle limit by separating functionality across two or more chiplets, enabling us to increase performance, and reduce die size and cost. High bandwidth and power-efficient interconnects between chiplets, using technologies such as through-silicon vias and hybrid bonding, enable the heterogenous system to operate with comparable efficiencies as monolithic integrated circuits.
Hybrid bonding (HB) is essential for this transition, as it offers high I/O connectivity with fine pitch ( < 10µm), increases system level bandwidth and speed, and improves thermal budget. Die-to-Wafer (D2W) HB further offers the benefit of using known-good-die to achieve higher yield, especially for heterogeneous integration.
Die-to-die (D2D) or D2W HB has many challenges. We will present results from a repeatable process with low contact angles, no degradation of dielectric roughness, and Cu dishing performance achieved with state-of-the-art systems at the Applied Materials Hybrid Bonding Centre of Excellence.