As the ability to shrink CMOS devices efficiently in two dimensions is becoming more cost-prohibitive, it is clear the semiconductor industry is entering an era of vertical scaling. The memory industry has shown how increased value can be acheived by accessing the third dimension, however this will be a much more complex feat for the logic industry. With stacked nanosheet transistors quickly becoming the norm at the leading edge, innovations beyond that will involve stacking transistors, and even whole chips, on top of each other. With the added complexity of High-NA EUV lithography as the defacto advanced patterning technology, this will result in an overall shift toward process simplification, hyper process control, and routine use of chiplet technology in overall chip design.